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Si5040
Register 47. RxtpTargetErr
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 1111 1111
RxtpTargetErr[7:0]
R/W
Bit
Name
Function
7:0
RxtpTargetErr[7:0] Receiver Test Pattern Checker Target Error Count.
If the value in the RxtpChkErrCnt register (register 53) exceeds this target error
count, an interrupt will be generated. The value is represented as an 8-bit floating
point number.
Mantissa = bits[7:4]
Exponent = bits[3:0]
Error count = (Mantissa/16) x 16 Exponent
0000 0000 = 0 (decimal)
1111 1111 = (15/16) x 16 15 (decimal)
Note: This register value does not represent a target bit error rate (BER). Rather, it is a target
bit error count for the period defined by tpTimeBase[1:0].
Register 48. RxtpChkErrCnt (LSB of a 40-bit Register)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = undefined
RxtpChkErrCnt[7:0]
R
Bit
Name
Function
7:0
RxtpChkErrCnt[7:0] Receiver Test Pattern Checker Error Count.
When using a defined timebase, this register holds the error count from the last com-
pleted timebase. In the continuous timebase setting, the register holds the current
running error count. Reading the least significant byte (LSB) latches the upper bytes.
Rev. 1.3
69
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